1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to the formation of metallization layers of reduced permittivity by using low-k dielectric materials.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and a plurality of inter-level connections, also referred to as vias, which provide the electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnect structures.
Due to the ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, highly conductive metals, such as copper and alloys thereof, in combination with a low-k dielectric material, have become a frequently used alternative in the formation of metallization layers. Typically, a plurality of metallization layers stacked on top of each other is necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration. For extremely scaled integrated circuits, the signal propagation delay, and thus the operating speed, of the integrated circuit may no longer be limited by the field effect transistors but may be restricted, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased, which is accompanied by the fact that the metal lines have a reduced conductivity due to a reduced cross-sectional area. For this reason, traditional dielectrics, such as silicon dioxide (k>3.6) and silicon nitride (k>5), are replaced by dielectric materials having a lower dielectric constant k, which are therefore also referred to as low-k dielectrics, having a relative permittivity of 3.0 or less. The reduced permittivity of these low-k materials is frequently achieved by providing the dielectric material in a porous configuration, thereby offering a k value of significantly less than 3.0. Due to the intrinsic properties, such as a high degree of porosity, of the dielectric material, however, the density and mechanical stability or strength may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride.
During the formation of copper-based metallization layers, a so-called damascene or inlaid technique is usually used, due to copper's characteristic of substantially not forming volatile etch products when being exposed to well-established anisotropic etch ambients. In addition, copper also may not be deposited with high deposition rates on the basis of well-established deposition techniques usually used for aluminum, such as chemical vapor deposition (CVD). Thus, in the inlaid technique, therefore, the dielectric material is patterned to receive trenches and/or vias, which are subsequently filled with the metal by an efficient electrochemical deposition technique. Moreover, a barrier layer is usually to be formed on exposed surface portions of the dielectric material prior to filling in the metal, which provides the desired adhesion of the metal to the surrounding dielectric material and also suppresses copper diffusion into sensitive device areas, as copper may readily diffuse in a plurality of dielectric materials, in particular in porous low-k dielectrics.
In some conventional approaches, the process of filling in a conductive metal, such as copper, may be accomplished in a so-called dual damascene strategy, in which the via opening, connecting to an underlying metal region, and a corresponding trench may be filled in a common deposition process, thereby enhancing the overall process efficiency. For this purpose, contrary to single damascene process techniques, in which a first portion of the dielectric material may be deposited and may be subsequently patterned so as to receive a via, which is then filled by the metal material, followed by the deposition of a further layer portion that receives the metal line, the via opening and the trench are formed in the dielectric material of the respective metallization layer and subsequently the barrier material and the copper material are filled in a common process sequence. For example, after the deposition of an appropriate dielectric material, for instance a low-k dielectric material, which may be provided at least partially as a porous low-k dielectric material, a patterning sequence is performed, wherein, in some illustrative approaches, the via opening is formed first, followed by a patterning of a trench in the upper portion of the dielectric material. Consequently, in this approach, the patterning of the trenches has to be accomplished on the basis of a surface topography including the previously formed via openings, which may be accomplished by planarizing the surface topography prior to lithographically patterning an etch mask for the trench etch process. Upon a continuous shrinkage of the overall feature sizes of sophisticated semiconductor devices, it appears, however, that the etch fidelity during the patterning of trenches, in particular at locations around the previously formed via openings, may be reduced, thereby also resulting in a reduced performance of the finally-obtained metallization system, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage, in which one or more metallization layers are to be formed above a device level of the semiconductor device 100. In the manufacturing stage shown, the semiconductor device 100 comprises a substrate 101, which, for convenience, is to be considered as an appropriate carrier material having formed thereon one or more material layers for receiving semiconductor circuit elements, such as transistors, capacitors, resistors and the like, which, for convenience, are not shown in FIG. 1a. For instance, the substrate 101 may represent a semiconductor material, for instance, a silicon material in combination with an appropriate silicon-based layer in and above which transistor elements may be formed. In other cases, a buried insulating layer (not shown) may be formed between the substrate material and the corresponding “active” silicon-based material layer, thereby providing a silicon-on-insulator (SOI) configuration. The circuit elements provided in the device level of the semiconductor device 100 may have critical dimensions of approximately 50 nm and less, depending on the device requirement. Above the substrate 101, including the semiconductor circuit elements, a metallization system is provided which may be represented by a first metallization layer 110 comprised of a dielectric material 111, which may be provided in the form of a conventional dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride and the like, depending on the overall device and process requirements. In sophisticated applications, the dielectric material 111 may comprise a low-k dielectric material to reduce the overall parasitic capacitance between adjacent metal regions. Furthermore, the metallization layer 110 may comprise a metal region, for instance, in the form of a metal line 112 which may comprise a highly conductive metal, such as copper, in combination with a barrier material, which in turn may include two or more layers, such as tantalum, tantalum nitride and the like, in order to obtain the desired barrier and adhesion effect. For example, tantalum nitride may provide enhanced adhesion to the surrounding dielectric material, while tantalum may provide superior copper diffusion blocking effects while also endowing enhanced mechanical stability to the copper material of the metal region 112. The metallization layer 110 may further include a cap layer 113, which may be comprised of silicon nitride, silicon carbide, nitrogen-containing silicon carbide and the like, wherein the cap layer 113 may act as an etch stop layer during the further processing of the device 100 and may also confine the metal line 112, for instance, in view of undue copper diffusion and any interaction of reactive components, such as oxygen, fluorine, with the highly reactive copper material in the metal line 112.
Furthermore, in the manufacturing stage shown, a further metallization layer 120 may be provided in an initial stage, that is, a dielectric material 121 is provided with appropriate material characteristics and a desired thickness so as to receive a via opening and a trench in a subsequent manufacturing stage. For instance, in sophisticated applications, the dielectric material 121 may comprise a low-k dielectric material having a reduced density, for instance, provided by a porous structure so as to obtain moderately low values for the dielectric constant, as may be required for further reducing the overall signal propagation delay in the metallization system of device 100.
Typically, the device 100 as shown in FIG. 1a may be formed on the basis of well-established process techniques. For example, the circuit elements (not shown) may be formed on the basis of well-established sophisticated process techniques so as to obtain the circuit elements with feature sizes as required by design rules of the technology node under consideration. After forming an appropriate contact structure (not shown), that is, an inter-layer dielectric material having a planarized surface topography for enclosing and passivating the circuit elements, including appropriate conductive elements connecting to contact areas of the circuit elements, the one or more metallization layers 110, 120, may be formed. For this purpose, the dielectric material 111 may be deposited and may be subsequently patterned to receive vias and/or trenches, followed by the deposition of the barrier material 112 which may be accomplished by sputter deposition, CVD and the like. It should be appreciated that the metallization layer 110 may be formed by similar process techniques, as will be described with reference to the metallization layer 120, depending on the overall process strategy. Thereafter, the metal, such as copper, may be filled in, for instance, by electroplating, where, prior to the electrochemical deposition process, a conductive seed layer, such as a copper layer, may be formed by appropriate deposition techniques, such as sputter deposition, electroless plating and the like. After filling in the copper material, any excess material thereof may be removed, for instance, by electrochemical etching, chemical mechanical polishing (CMP) and the like. Next, the cap layer 113 may be formed by depositing one or more appropriate materials, such as the materials previously explained, on the basis of well-established plasma enhanced chemical vapor deposition (PECVD) techniques. Subsequently, the dielectric material 121 may be formed by any appropriate deposition technique, such as CVD, spin-on processes and the like, which may be accompanied by further reducing the relative permittivity of the material 121 by a subsequent treatment so as to create enhanced porosity therein, for instance, by incorporating an appropriate material, so-called porogens, which may result in enhanced porosity after treating the material 121, for instance, by heat, radiation and the like. For this purpose, well-established process recipes are available. Consequently, due to the significantly reduced relative permittivity, which is typically associated with a reduced density of the dielectric material under consideration, which may be even further enhanced by a desired high degree of porosity, the material 121 may suffer from increased diffusion of more or less volatile components that may come into contact with the material 121 at subsequent process stages.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which a via opening 121A is formed on the dielectric material 121. For this purpose, sophisticated patterning regimes are typically applied, which involve the deposition of any appropriate materials, such as anti-reflective coating (ARC) materials, resist materials and the like, which may then be lithographically patterned to form an appropriate etch mask for a subsequent anisotropic etch process. That is, during the actual etch process, sophisticated conditions may be encountered wherein the aspect ratio of the opening 121A may be substantially determined by the thickness of the layer 121 in combination with the thickness of any mask material, such as the ARC material, which may act as a hard mask, and the resist material, depending on the overall process strategy. For example, for a lateral dimension of the opening 121A of approximately 200 nm or even less, and for a thickness of the layer 121, in combination with the thickness of the mask material, which may be in the range of several hundred nanometers or more, the aspect ratio, i.e., the ratio of the depth of the opening 121A and the lateral dimension thereof, may be 5 or even more, depending on the overall process requirements. Consequently, the etch process, which may be controlled on the basis of the cap layer 113, may require enhanced overall process control in order to obtain the openings 121A so as to comply with design rules. Moreover, after removal of the etch mask, the surface topography of the metallization layer 120 may comprise a plurality of high aspect ratio openings, such as the openings 121A, which may also represent a challenge for a subsequent critical patterning process for forming trenches in an upper portion of the dielectric material 121.
FIG. 1c schematically illustrates the semiconductor device 100 with a planarization layer 102 formed in the via opening 121A and on the dielectric material 121. According to well-established process techniques, the planarization layer 102 may be comprised of an organic material, such as a polymer material and the like, which may be deposited on the basis of a highly non-conformal deposition technique, such as spin-on techniques, possibly in combination with further planarization steps, such as CMP, in order to fill the opening 121A and also provide enhanced surface conditions during the subsequent lithography process, in which a resist material may be provided to form a mask for a trench to be etched into the upper portion of the dielectric material 121. The planarization layer 102, which may also act as an ARC material, may be in direct contact with the dielectric material 121. During the interaction of these materials, it is believed that components, such as the solvent of the organic planarization layer, may diffuse into the dielectric material 121, in particular when a more or less porous structure thereof may have a reduced diffusion blocking effect.
FIG. 1d schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which an etch mask 103 is used for patterning the planarization layer 102 and the underlying dielectric material 121 during an etch process 104. As previously discussed, for sophisticated devices, a width of a trench 121C may be on the order of magnitude of several hundred nanometers to approximately 100 nanometers and less, depending on the device level and the technology node under consideration. Since the lateral width and the depth of the trench 121C represent important aspects for adjusting the overall performance of the metal line to be formed in the trench 121C, enhanced process control is required to obtain uniform metallization characteristics. That is, the width and depth of the trench 121C substantially determine the cross-sectional area of a respective metal line, the performance of which is substantially determined by the characteristics of the metal to be filled in, the electromigration performance of respective interfaces and the cross-sectional area available for conducting current in the respective metal line. As previously indicated, increased diffusion of components of the planarization material 102 into the volume of the dielectric material 121, in particular in the vicinity of the via opening 121A, as indicated by a portion 121B, may result in a non-uniform etch behavior, thereby resulting in a less predictable fidelity during the etch process 104 which might finally translate into reduced performance of the respective metallization systems, in particular when sophisticated semiconductor devices are considered that are formed on the basis of low-k dielectric materials having an enhanced degree of porosity while also requiring metal lines and vias of reduced lateral dimensions.
After finishing the etch process 104 and removing the etch mask 103 and the planarization material 102 and opening the cap layer 113 within the via opening 121A, an appropriate barrier material, such as tantalum nitride in combination with tantalum, may be deposited and subsequently copper may be filled in in a common process sequence, thereby efficiently forming a via and a metal line on the basis of the opening 121A and the trench 121C. However, as indicated above, although an efficient process flow may be accomplished by using the above-described sequence, increased variability of metal line characteristics may be observed, in particular in combination with low-k dielectric materials having a porous structure, which may render these techniques including a common metal fill process as less attractive in view of further device scalability.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.